Power semiconductor devices are currently being used in many applications, either as discrete components or integrated with other transistors as an integrated circuit. Such power devices include high-voltage integrated circuits which typically include one or more high-voltage transistors, often on the same chip as low-voltage circuitry. A commonly used high-voltage component for these circuits is a laterally diffused metal oxide semiconductor (LDMOS) transistor. High-power applications have called for the use of such lateral double diffused MOS transistors primarily because they possess lower “on” resistance, RDS (on), faster switching speed, and lower gate drive power dissipation than their bipolar counterparts. However, these devices have heretofore also been strongly associated with bi-polar based process flows when integrated into a Bi-CMOS environment.
LDMOS transistors used in the high-voltage integrated circuits may generally be fabricated using some of the same techniques used to fabricate low voltage circuitry or logic circuitry. In general, LDMOS structures are fabricated in a thick epitaxial layer of the same or opposite conductivity type as the substrate. The epitaxial layer helps to equally distribute the applied drain voltage laterally across the silicon surface.
Typically, in a step subsequent to the formation of the epitaxial layer, a gate structure is formed over the epitaxial layer and a drain region dopant, such as phosphorous or arsenic, is laterally diffused under the gate structure. Diffusing the drain region dopant generally requires a masking step that masks all regions of the device except for the drain region and the gate structure. In addition to laterally diffusing the drain region dopant, a source region dopant, such as boron, is laterally diffused under the other side of the gate structure. An additional masking step, similar to the masking step previously described, is also required when laterally diffusing the source region dopant. Subsequent to laterally diffusing the source and drain region dopants, a higher concentration dopant may be diffused within the device.
The previously described method of manufacturing an LDMOS device is extensively used and well accepted, however, it experiences certain drawbacks. One drawback currently experienced during manufacturing LDMOS devices is an uncontrollable diffusion of the boron implant, resulting from variations in a desired implanted profile. Typically, the problem is a result of the fairly high kinetic energy imparted on the boron implanted atoms, and collisions that occur between such atoms in a lattice of the substrate material. These collisions tend to cause a portion of the boron implanted atoms to locate in an undesirable region of the device in a process called channeling. Typically the uncontrollable diffusion occurs in both the vertical and horizontal planes resulting in a structure that is substantially different than designed. The uncontrollable diffusion, if extreme enough, may also cause device failure.
Accordingly, what is needed in the art is a method of manufacturing an LDMOS device that does not experience the uncontrollable diffusion issues associated with the prior art methods of manufacturing LDMOS devices.